1. Field of the Invention
This invention relates to a semiconductor device with input protection circuit for protecting it from external surge due to static charge into the input terminal.
2. Description of the Prior Art
Semiconductor devices, especially MOS ICs and Bi-CMOS ICs, have a gate insulating film consisting of a silicon oxide film extremely thin between about 20 and about 30 nm in thickness. This may be cause that external static charge and noise easily brings about breakdown in the gate-insulating film. It therefore is essential to provide a semiconductor device with a semiconductor input protection device.
An early type of semiconductor input protection device was provided with an input protection resistance between input terminal and internal circuit, and thereby external surge was modified according to the time constant determined by the value of the input protection resistance and the stray capacity associated with the input protection resistance, and others.
As the next-generation type of semiconductor input protection device, combined use of input protection resistance and protective MOS transistor came. The protective MOS transistor had a protective-function capacity instead of the stray capacity. Besides it effected the function of letting surges of 20 V or higher pass to the ground. Protective MOS transistor can be grouped into two types: In the first, the drain and the gate electrode are connected to the input terminal and the source to the ground, and the field oxide film is used instead of the gate insulating layer. (The first type protective MOS transistor is referred to as V.sub.T2 type transistor, hereinafter.) The second type has the same in structure as a MOS transistor constituting an internal circuit component, in which the drain is connected to the input terminal, and the source and the gate electrode to the ground. (The second type protective MOS transistor is referred to as V.sub.DS type transistor, hereinafter.) A typical semiconductor input protective device comprising these protective elements was constructed as follows: the input terminal was connected to the first terminal of the first impurity diffusion layer resistance, which was a first input protective resistance, and to the gate electrode of a V.sub.T2 type transistor. The second terminal of the first impurity diffusion layer resistance was connected to the first terminal of the second impurity diffusion layer resistance, which was a second input protective resistance, and to the drain of a V.sub.T2 type transistor. The second terminal of the second impurity diffusion layer resistance was connected to the drain of the BV.sub.DS type transistor and to the internal circuit. The sources of V.sub.T2 type and BV.sub.DS type transistors and the gate electrode of the BV.sub.DS type transistor were connected to the grounded wire. In this case, however, a MOS transistor of a small current capacity was used for letting external surge to pass to the ground, and therefore a part of external surge to pass to the ground, and therefore a part of external surge, when large, was allowed occasionally to reach the internal circuit.
Thus recently punch-through transistor large in current capacity has become used as a protective component in semiconductor input protection devices. The punch-through transistor functions to clamp relatively large surges while conventional protective elements serve against relatively small ones.
A semiconductor input protection device of such type is exemplified in U.S. Pat. No. 4,819,046 (corresponding to Japanese Patent Laid-Open Application No. Sho. 62-274664) in which a punch-through transistor consisting of a pair of impurity diffusion layers is interposed between the first terminal of the first impurity diffusion layer resistance, a first input protection resistance, and the input terminal. This punch-through transistor is constructed as follows: The first impurity diffusion layer is connected to the input terminal, the second impurity diffusion layer is connected to a ground or power supply potential node. A field oxide film is formed on the semiconductor substrate comprising the first and second impurity diffusion layers which are adjacent to a channel stopper and formed simultaneously with the first input protection resistance and the source and drain of a MOS transistor in the internal circuit.
In the punch-through transistor like this, the first and second impurity diffusion layers contact with the channel stopper, and therefore when external surge is input into the first impurity diffusion layer, the depletion layer of the first impurity diffusion layer in the region of the semiconductor substrate between the first and second impurity diffusion layers (the channel region of the punch-through transistor) results, in turn, in greater extension in the inside of the semiconductor substrate than at the interface between the semiconductor substrate and the field oxide film, and in higher punch-through current density in the inside of the substrate than at the interface than. Thus more incomplete crystallization at the interface due to large current is avoidable, that is, this construction does not allow the punch-through current to be a cause of interfacial leakage. On the other hand, the formation of p-n junctions where the first and second impurity diffusion layers and the channel stopper contact with each other gives a tendency toward local occurrence of junction breakdown due to external surge especially in the surrounding of the first impurity diffusion layer. Local junction breakdown, if it occurs, would result in injection of hot carriers into the field oxide film surrounding the first impurity diffusion layer, and in reduction of the depletion layer in the first impurity diffusion layer locally at the interface of the semiconductor substrate adjacent to the injected portion. Thus, still after external surge has passed into the semiconductor substrate, tendency toward local leakage remains in the affected portion. Once such situation comes, it can function as a semiconductor input protection device against external surge but normal inputs into the internal circuit from the input terminal would be inhibited by such leakage.
Another example of semiconductor input protection device with a punch-through transistor is disclosed in Japanese Patent Laid-Open Application No. Hei. 1-194474, in which a well-type punch-through transistor consisting of a pair of wells is connected to the input terminal. This is a proposal for solving the problem with the injection of hot carriers into the field oxide film surrounding the first impurity diffusion layer, resulting from junction breakdown, and its construction is as follows: The first impurity diffusion layer connected to the input terminal is formed in the first well layer, and the second impurity diffusion layer connected to a ground node is formed in the second well layer. The first and second well layers are defined at specified distances from the channel stopper. Somewhere except the connection point of the input terminal with the well-type punch-through transistor, the internal circuit is connected to the input terminal through the first impurity diffusion layer resistance, and others. The first well layer is defined at a specified distance from the channel stopper, and thereby junction disruptive strength of the first well layer is higher than that of the first impurity diffusion layer resistance. If external surge passes into the input terminal, this would not allow junction breakdown to occur in the well-type punch-through transistor to occur, it can occur in the first impurity diffusion layer resistance. Besides the well-type punch-through transistor is high in punch-through voltage and current compared with the first example.
A problem of this semiconductor input protection device however resides in that the area required for the input terminal is larger than the above-mentioned first example of input protection device, this resulting from that the connection between the first impurity diffusion layer resistance connecting to the internal circuit and the input terminal is made somewhere other than the connection point between the well-type punch-through transistor and the input terminal. Another problem with this input protection device is that owing to the absence of channel stopper between the first and second well layers in the semiconductor substrate, punch-through current density is uniform in the longitudinal direction, resulting, in turn, in larger current-flow also at the substrate interface, more incomplete crystallization at the substrate interface, and tendency toward interfacial leakage.